1. Field of Invention
The present invention relates to a test apparatus.
2. Description of the Related Art
Serial data transfer is used to transmit and receive data between semiconductor circuits via relatively few data transmission lines. Clock and data recovery (CDR) or source synchronous clocking is used in serial data transfer. In CDR, 8B10B encoding or 4B5B encoding is used to encode serial data such that the data does maintain the same value continuously for a predetermined period of time or longer. A clock for synchronization is embedded in the serial data.
In testing a semiconductor circuit designed to output serial data as a device under test (DUT), a CDR circuit is provided at the input stage of a semiconductor test apparatus (sometimes simply referred to as test apparatus). The CDR circuit extracts from the serial data a reference clock signal. The circuit generates a strobe signal based on the clock signal thus extracted and latches the bit data of the serial data accordingly. The test apparatus compares recovered data with expected values that the data should take so as to determine whether the DUT is defective or not. Patent documents 1 and 2 disclose a related technology.
For example, patent document 2 discloses a CDR circuit where a phase locked loop (PLL) is used. In this circuit, the oscillation frequency of a voltage controlled oscillator is controlled so that the phase of a clock signal accompanying the serial data matches the phase of the strobe signal generated based on the clock signal. As a result, the phase of the strobe signal can be adjusted to track the jitter of the serial data.
In one of the methods of testing a DUT, a margin test is performed in which a timing margin or an amplitude margin is tested. In other words, the phase of the strobe signal recovered by CDR is shifted gradually in predetermined steps, as the serial data from the DUT is latched (captured). A determination of pass or failure is made for each phase. Alternatively, the threshold voltage for determination of the level (0 or 1) of the serial data is changed between a plurality of levels, as the serial data from the DUT is latched (captured). A determination of pass or failure is made for each level. By performing margin tests using a plurality of parameters (e.g., combinations of timing and amplitude), a Shmoo plot where passes and failures are plotted can be produced for each of the combinations of parameters organized as a matrix.
When the timing of output of serial data from the DUT varies temporally, the hunt function is taken advantage of. The hunt function identifies the timing of data output from the DUT by embedding a predetermined pattern at the head of the serial data and detecting the predetermined pattern in the test apparatus. After identifying the head position in the serial data using the hunt function, the test apparatus starts comparing the serial data with the expected value pattern (see patent document No. 3).    [patent document No. 1] JP H2-62983    [patent document No. 2] JP 2007-17257    [patent document No. 3] JP 2006-3216    [patent document No. 4] JP 2008-28628
It will be assumed that the aforementioned margin test is performed in a test apparatus provided with the hunt function. In this case, the hunt function may not work properly due to the failure to capture the header pattern properly, if the timing of capturing data or the threshold voltage for level determination is changed in a margin test. Failure to identify the position of the header pattern properly results in an offset between the cycle of serial data from the DUT and that of expected value pattern, making it impossible to give a determination of pass or failure properly. Such a problem may also be caused in performing a test other than a margin test.